- SRAM-based FPGAs can also be reprogrammed while in the system, which makes in-field upgrading very easy. - Also, SRAM-based FPGAs can be used for reconfigurable computing, a concept whereby computers contain FPGAs and algorithms can be compiled to run in the FPGAs.. - That’s because every semiconductor company in the world knows how to make SRAMs. - Because an antifuse FPGA is programmed once, the program and the design are safe from prying eyes.. - In recent years, some compa- nies have begun offering different variations of the concept in actual products. - And a synthesis program doesn’t need to partition the code between hardware and software — all of the HDL code represents hard- ware. - Also, hardware designers still need to set switches within comments in the code and change settings of the synthesis program, in order to get usable results. - And after all of this, the designer often needs to tweak the HDL code to fit the design into the FPGA and to meet the required performance criteria.. - Some of the solutions include libraries of algorithms that have already been developed, tested, and synthesized and that can be called from soft- ware. - You can then debug the design using real world hard- ware and real world software. - You can stop and start the hardware emulator in order to examine internal nodes of the design. - You can make changes to the design to correct mistakes or to improve performance, before the design is committed to silicon.. - Of course, a hardware emula- tor runs at a fraction of the speed of the final chip, but it affords a form of testing that is otherwise not possible, except with prototyping.. - Many of them, though, use large sets of FPGAs to emu- late the chip design, because FPGAs allow users to easily load and modify designs, stop the design while it is in the system, and easily examine internal nodes and external I/O.. - If the design cannot fit into a single FPGA, a board can be designed that contains several FPGAs into which the chip design is partitioned.. - FPGA prototypes are generally cheaper than hardware emulators, but you must do all of the work, including partition- ing the design, designing the board to hold the FPGAs, and designing whatever debug capabilities you require.. - Knowledge of the internal architecture of FPGAs and the semiconductor tech- nologies used to implement the programmable elements is critical for consider- ing which FPGA to use in your design. - Configurable logic blocks — Although most FPGAs have similar logic blocks, there are differences, for example, in the number of flip-flops and the width of the lookup tables. - The number of CLBs in the device — This will determine how much logic the device can hold and how easily your design will fit into it.. - Emulating and prototyping ASICs — FPGAs can be found in off-the-shelf hardware emulators for testing the design of an ASIC in a real-world target before it goes to silicon. - Table 3.2 shows a summary of the characteristics of each type of programmable device. - “medium,” and “high” for some of the characteristics. - Select all of the parts of a typical FPGA architecture.. - (b) TRUE or FALSE: Configurable I/O blocks contain flip-flops on the outputs to enable the designer to decrease the clock-to-output times of the outputs.. - (c) TRUE or FALSE: FPGA programmable interconnect consists of lines that start at one end of the chip and continue to the other end to enable all CLBs to be connected.. - Select TRUE or FALSE for each of the following statements about SRAM-based FPGAs and antifuse FPGAs:. - Even in companies that followed a defined procedure, often parts of the procedure were not well understood or completely imple- mented. - For example, a company might emphasize the design process and not under- stand the testing process.. - The goals of the Universal Design Methodology are these:. - Works reliably over the lifetime of the device. - In the least amount of time. - Plan the design efficiently, meaning. - Create a reasonable schedule as early in the process as possible. - 4.1.2 The Design Flow of UDM-PD. - The design flow consists of the steps shown in Figure 4.1. - Description of the I/O pins, including:. - Market changes may require changes in the specification. - This diagram will help describe the overall functionality of the device and will be a good reference for the system designers, PC board designers, designers of other chips in the system, and software developers.. - The internal block diagram will be the starting point for the behavioral descrip- tion of the device. - 4.2.3 Description of the I/O Pins. - The device that you choose is often restricted by the requirements of the I/O pins. - The electrical characteristics of the I/O will determine which vendors and which technologies can be used.. - Typically, two or three of the best engineers in the department were assigned to a single chip. - One of the chips that needed to be designed was a simple buffer between a board and a backplane. - The logic requirements of the design were extremely simple, but the current drive requirements — 48 mA per signal for 8 signals — was more than most ASIC vendors could produce at the time. - At the end of the design review, one of the engineers at the company adamantly stated that we should demand that NCR meet the specifications that we had written. - You should have a good understanding of the clock frequency required for the design and also the setup and hold time requirements of the I/O.. - (These requirements are determined by the interface between your device and the other chips in the system.). - Package type is often a very large percentage of the entire cost of an FPGA.. - When they add up the worst-case power consumption numbers for all of the parts in the system, they end up with a number so large that it seems unreasonable. - Therefore, to get a realistic number of the best-case, typical-case, and worst-case power consumption for a system, use the following formulae (which are standard formulae for the mean and standard devi- ation of a discrete random variable):. - At the end of the specification phase, it is very important to have a design review. - Once a specification has been written, the design team can use it to find the best vendor with a technology and price structure that best meets their requirements.. - The founder of the company, an engineer, had been kicked out by the investors. - The senior members of the engineering team, maybe three or four people, left with him. - The software engineers told me that the new Vice President of Engineering had changed all of the priorities so that the test code was dead last on the list.. - It was difficult because I didn’t understand all of the software running on this system. - I showed this to the VP and to the CEO of the company. - Verification is a “super-phase” because it consists of several other phases of the design process. - some kind of simulation will be performed as part of nearly every stage of the design process. - Small sections of the design should be simulated separately before hooking them up to larger sections, as described in Chapter 7. - Once design and simulation are finished, another design review must take place so that other engineers can check the design. - This is one of the most important reviews because only with correct and complete simulation will you know that the chip will work correctly in your system.. - In addition to the chip design team, you should invite engineers who were not involved in the actual chip design to this review. - These out- siders can also suggest corner cases that were not already simulated that will often uncover additional problems in the design.. - After synthesis, the chip must be resimulated using the gate level output of the synthesis tool. - Whichever method is used, the design team will need to address any discrepancies. - I finally decided to hold a specification review — something that I then realized should have been held at the beginning of the project. - Demoralized about my new project, I continued with the company long enough to get the chip design on the right track and put it in the hands of my colleague. - The design was fully documented, a rarity at this company, and I left to find other work. - Later I found out that the design was cancelled right before production because someone higher up found out that no one really wanted to buy it.. - The software will figure out the bits needed to program the chip to implement the design. - If you cannot successfully place the design into the device and route it, you may need to tweak the design. - If you have followed all of the procedures outlined in this book, the chances of a major problem at this stage, resulting in a major design change, will be minimized.. - Once the place and route is successful, the design team must perform timing analysis. - Typically, the design team will need to redesign and resimulate certain paths in order to get the correct timing. - In some cases, they will need to change functionality, or they will need to change the timing specifications of the chip, in order to get the design to work.. - At this stage, the design team must check the results of synthesis to make sure that the RTL design that was fully simulated is functionally equivalent to the gate level design that was produced after synthesis. - In some cases, it may also be necessary to show that the configuration of the programmable device behaves identically to the RTL description. - The most common method of determining that the input circuit and the final cir- cuit are correct is to resimulate the final circuit using all of the tests that were used to simulate the original circuit. - This software performs a mathematical comparison of the functional- ity of both circuits in order to confirm that both circuits will operate correctly.. - The final review of the chip should be a formality at this point. - If the design team has followed all of the other steps and the other reviews have taken place, this review should be a simple sign-off that verifies that the design has been coded, simulated, synthesized, laid out and routed, and is now ready to go into the system.. - The design team can often work around these minor problems by modifying the system or changing the system software. - The team needs to test and document these prob- lems so that they can fix them on the next revision of the chip. - System integra- tion and system testing is necessary at this point to ensure that all parts of the system work correctly together.. - works reliably over the lifetime of the device. - in the least amount of time. - create a reasonable schedule as early in the process as possible. - know all necessary resources up front and allocate them as early in the process as possible. - In this chapter, we have also studied the design flow that is associated with UDM-PD. - Simulating the design. - Synthesizing the design. - Place and route of the design. - (d) Design a device that works reliably over the lifetime of the device. - (e) Allocate a maximum number of resources in the minimum amount of time (f) Plan the design efficiently. - UDM is a methodology to design a device efficiently, meaning (choose all that apply) (a) In the least amount of time. - (b) Knowing all necessary resources up front and allocating them as early in the process as possible. - (c) Creating a reasonable schedule as early in the process as possible (d) Planning to ship products while testing the design. - Put each phase of the design flow in the correct order.. - (a) The name of the FPGA vendor. - (b) A description of the I/O pins, including output drive capabilities and input threshold levels. - Note that EDA tools that enable many of the techniques in this chapter are described in detail in Chapter 7.
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