- Listing B.8 Figure 5.9. - Listing B.8: Figure 5.9 195. - glitch Listing B.8 Figure 5.9 (Continued). - Listing B.10: Figure 5.11 197. - no_glitch Listing B.9 Figure 5.10 (Continued). - Listing B.10 Figure 5.11. - Listing B.11: Figure 5.12 199. - Listing B.10 Figure 5.11 (Continued). - Listing B.11 Figure 5.12. - This is an enable flip-flop.. - Listing B.12 Figure 5.15. - Listing B.12: Figure 5.15 201. - DESCRIPTION: This module defines a circuit that can. - Listing B.12 Figure 5.15 (Continued). - Listing B.13 Figure 5.16. - DESCRIPTION: This module defines a circuit that can still. - Listing B.13: Figure 5.16 203. - Listing B.13 Figure 5.16 (Continued). - ABEL — An early hardware description language used to program PALs.. - A cer- tain amount of current during program- ming of the device causes the two sides of the antifuse to connect.. - architecture — A chip architecture refers to the high level structure of the chip.. - asynchronous — An asynchronous design is any design that breaks a rule of syn- chronous design. - An asynchronous design has delays that are not strictly controlled by a clock and therefore can- not be easily controlled and predicted.. - This is a method of including test generation and moni- toring circuitry in a chip design so that the chip can perform tests on itself to determine whether it is still working correctly.. - In 1939, Claude Shannon wrote his revolutionary Master's thesis A Symbolic Analysis of Relay and Switching Circuits that described for the first time how Boolean algebra could be applied to the design of com- puters.. - boundary scan — Boundary scan uses the scan methodology but scans only nodes around the boundary of the chip, not internal nodes. - This is effective for test- ing the FPGA's connections to the cir-. - In a “fine-grained” architec- ture, more like a true gate array ASIC, the CLB will contain only very basic logic. - combinatorial logic — This is the term for logic that implements Boolean equa- tions and does not have any reliance on timing or sequencing.. - core — The basic circuit of a specific func- tion, excluding any extraneous circuits such as I/O buffers that would be found on a physical chip. - CRC — Cyclic redundancy check — an error detecting technique used to ensure the accuracy of digital data transmissions.. - The transmitted messages are divided into predetermined lengths, called frames, and a special code is appended to the end of each frame. - CUPL — An early hardware description language used to program PALs.. - decay — Decay refers to the amount of time it takes for a signal to go from an unstable state to a stable one.. - DFT — Design for test — This is the practice of designing an FPGA with test circuitry included from the beginning.. - ECL — Emitter coupled logic — a common type of circuit for implementing logic functions that have very fast switching times.. - EDA — Electronic design automation refers to tools for designing electronic devices.. - EEPROM — Electrically erasable PROMs are read-only memories that can be pro- grammed and erased using a higher voltage than that used in normal opera- tion.. - EPROM — Erasable PROMs are read-only memories that can be programmed with an electric current, but are erased using prolonged exposure to ultraviolet light.. - flash EPROM — Flash EPROM can be elec- trically programmed. - FPGA — Field Programmable Gate Arrays are programmable chips that are struc- tured very much like a gate array ASIC.. - Sequences of values can then be scanned into and out of the chain in order to test the FPGA.. - functional simulation — This term refers to simulating a design without considering actual timing numbers. - glitch — An unexpected signal or short duration.. - hold time — This is the amount of time that a signal on the input to a clocked device must be stable after a clock edge in order to guarantee that the clocked device will capture the correct value.. - in-system programmability — The ability to reprogram a programmable device while it is soldered in a system and the system is powered up. - SRAM-based devices can be programmed in-system.. - EPROM-, EEPROM-, and Flash PROM–based devices can be pro- grammed in-system if the device includes the pins and internal circuitry to support this feature.. - IP — Intellectual property — the parts of a chip design that are considered unique and are protected by patent laws. - Usu- ally this refers to a particular function that has been designed and tested and can be purchased to be used in another design. - JTAG — Joint Test Action Group — This term is commonly used to refer to the IEEE Standard 1149.1, which defines a spe- cific form of boundary scan implemen- tation. - The name of the standard has come to be known by the name of the group that developed the standard, in the same way that the monster created by Dr. - large-grained architecture — In a large-grained FPGA, the CLB contains larger functionality logic. - LUT — lookup table — the small SRAM in a CLB of an SRAM-based FPGA that is used to implement Boolean logic.. - macrofunction — A macrofunction, or macro, is simply a large, predefined, tested circuit that can be used freely in different FPGA designs.. - metastability — Metastability refers to a state of an object that is stable, but any small disturbance to the object will. - Moore’s Law — The original statement of this “law” in 1965 was that the number of transistors per integrated circuit dou- ble every couple of years. - mux — This is simply the short name for a multiplexer.. - one-hot encoding — This is a method of designing state machines whereby each state is represented by a single flip-flop.. - encoding, which makes more efficient use of the “large-grained” CLBs in an FPGA, which are the only kind of FPGAs currently available.. - open drain — An output that can be driven to a low value or not driven at all. - PAL — Programmable arrays of logic are chips that are good for implementing state machines. - PALASM — An early hardware description language used to program PALs.. - PECL — Positive emitter coupled logic — a common type of circuit for implement- ing logic functions. - PLA — Programmable logic arrays are chips that are good for implementing combinatorial logic. - place — This refers to placing logic inside CLBs of an FPGA in order to imple- ment the FPGA design.. - Plan Nine from Outer Space — The worst movie of all time, directed by Ed Wood,. - For example, pragmas may alter the kinds of error messages that are gener- ated or optimize the design in some way.. - product terms — Terms in a Boolean equa- tion that are ANDed together.. - PROM — Programmable read only memory can be easily programmed with specific contents. - pseudorandom — This refers to a sequence of numbers that are predictable and repeatable, but are produced in such a way that they have the same character- istics and distribution as numbers that are selected randomly.. - race condition — A race condition occurs in an asynchronous circuit when the func- tion is dependent on which of two sig- nals get to a certain point first, and the winner of this race depends not on a controlled period of time, but the tim- ing characteristics of the circuit.. - RTL — Register transfer level — this is a level of description using a hardware description language (HDL) that describes circuitry in terms of clocks, Boolean equations, and registers.. - scan — Scan methodology involves creat- ing scan chains from the flip-flops in a design so that sequences of values can be scanned into and out of the chain in order to test the FPGA.. - scan chain — A scan chain is a structure where the output of each flip-flop in the chain is connected to the input of the next flip-flop in the chain. - In this way, sequences of values can be scanned into and out of the chain in order to test the FPGA.. - setup time — This refers to the amount of time before a clock edge that a signal must be stable on the input to a clocked device in order for the device to record the correct input value.. - signature — The signature of an FPGA refers to the pattern that is expected to be output from the chip after a long deterministic sequence of inputs.. - slew rate — The slew rate of a signal is a reference to how quickly it changes voltage.. - SOPC — System on a programmable chip — this term is used to describe a very com- plex and very dense programmable device, a CPLD or FPGA, that can con- tain so much logic that it can be consid- ered an entire system.. - SRAM — Static random access memory is memory that can be written and read numerous times while in the system. - static timing analysis — Static timing analy- sis is a process that looks at a synchro- nous design and determines the highest operating frequency of the design that does not violate any setup and hold times.. - sum terms — Terms in a Boolean equation that are ORed together.. - synchronous — Synchronous design adheres to the following rules:. - All data is passed through combi- natorial logic, and through delay elements (typically flip-flops) that are synchronized to a single clock.. - No signal that is generated by combinatorial logic can be fed back to the same combinatorial logic without first going through a synchronizing delay element.. - clocks must go directly to the clock inputs of the delay elements with- out going through any combina- torial logic.. - testbench — The simulation code that gen- erates stimulus to a design and exam- ines the outputs of the design.. - threshold — The threshold of a gate is the voltage value or range of the input at which the output begins to change value.. - timing simulation — Timing simulation involves including timing information in a functional simulation so that the real behavior of the chip is simulated.. - toggle coverage — When performing func- tional simulation, a rough estimate of the amount of simulation to perform is called toggle coverage, which measures the number of nodes in the FPGA that change state from 0 to 1 and from 1 to 0 during simulation as a percentage of the total number of possible state tran- sitions (two per node because each node can change from 0 to 1 and from 1 to 0).. - TTL — Transistor-transistor logic — a com- mon type of circuit for implementing logic functions in which the output is driven by two BJT transistors.. - He is also the founder and president of The Chalkboard Network ( www.chalknet.com. - See Chapter 2. - flash EPROM flip-flop . - See Chapter 3. - You get a cookbook with step-by-step in- structions and complete source code to the state-oriented framework. - Develop a solid understanding of the math behind common functions — and learn how to make your programs run faster and more efficiently! You get a solid course in applied math from the renowned columnist of Embedded Systems Programming Magazine — and a versatile set of algorithms to use in your own projects. - This edition shows the Web server porting to the PIC16F877 chip as well. - Learn the inner workings of an RTOS! This release of MicroC/OS adds documentation for several important new features of the latest version of the software, including new real- time services, floating points, and coding conventions
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