- 3.3.1 Don’t Care Conditions 68 3.3.2 The Complementary Approach 70 3.4 Quine – M C Cluskey Method 73. - r ¼ base or radix of the number system. - Example 1.2 The conversion of 11010101 to decimal would use the following steps:. - (ii) If a carry bit is produced by the leftmost bits (i.e., the sign bits), add it to the result.. - The decimal equivalent of the result is 2 2 4 þ 2 3 þ 2 2 þ 2 0 ¼ 2 3.. - shifted right (i.e., the number becomes 1101101), the decimal value of the original and the shifted number remains the same ( 2 19 in this case).. - In the 4221 code, the sum of the weights is exactly 9( ¼ 4 þ 2 þ 2 þ 1). - Perform the addition of the following binary numbers:. - Find the floating-point representation of the following numbers:. - FIGURE 2.1 Graphical form of the relation f(a, 1), (a, 4), (b, 2), (b, 3)g.. - “x divides y.” The relation R is antisymmetric, since x divides y and y divides x, which implies x ¼ y.. - For example, in Figure 2.4 the in-degree of vertex C is 2, the in-degree of vertex D is 1, and so on. - Example 2.3 The following expression can be represented in a simplified form using Theorem 10.. - This can be proved by deriving the complement of the function f (x, y, z) ¼ xy þ x¯z þ y¯z¯. - Derive the dual of the sum-of-products expression.. - The dual of the given expression is. - The sum-of-products form of the function is f (X, Y, Z) ¼ XYZ. - The product-of-sums form of the function is f (X, Y , Z) ¼ X Y Z þ XYZ þ X YZ. - The circuit representation of the NOT gate is shown in Figure 2.9. - When the switch is operated (i.e., X ¼ 1) the circuit is broken, causing the light to be off (i.e., f ¼ 0). - The truth table of the NOT circuit is shown in Table 2.6. - Derive the dual of the following Boolean functions:. - Find the complements of the following Boolean functions:. - Derive the truth table for each of the following circuits.. - Figure 3.2a shows the direct implementation of the expression.. - The decimal number corresponds to the minterm number of the Boolean function.. - Example 3.1 The Boolean functions represented by the Karnaugh map of Figure 3.8 can be reduced to. - The reduced form of the function can be derived directly from the Karnaugh map:. - Example 3.6 The minimized form of the Boolean function f (A, B, C . - f (A, B, C) ¼ (A þ C)(A þ B þ C)( A þ B) The complement of the function is. - The prime implicants of the function can be derived as shown in Figure 3.28. - is also a minimal form of the original function. - It can be verified from the Karnaugh map of the function (Fig. - Thus a minimal form of the Boolean function is. - Thus a possible cover of the above function is. - thus the PCN of the cube is. - The complement of the expression is. - To illustrate, let us derive the complement of the following function:. - Arrange the ON-set of the function as a matrix.. - Therefore the ON-set (i.e., the cover of the function) is C C 2. - Note that the cardinality of the reduced ON-set (i.e., the cover) is the same as the original cover of the function. - For example, in the following cover of the function f (a,b,c) ¼ ab þ a¯c þ ac¯ þ bc. - {don’t care set of the function} {a}. - hence C 4 can be removed from the cover of the func- tion. - The PCN representation of the cover of the function is a b c g d. - Figure 3.36 shows the Karnaugh map of the function after the REDUCTION step.. - Figure 3.37 shows the Karnaugh map of the function after the EXPAND step.. - Individual minimization of the functions results in the following shared terms:. - FIGURE 3.41 Multilevel implementation of the simplified expressions.. - Take the complement of the minimized expression.. - Take the complement of the complemented expression. - The complement of the expression for f¯ is then derived:. - The NAND – NAND realization of the above expression is shown in Figure 3.45.. - Then a NOR – NOR realization of the circuit can be obtained as shown in Figure 3.47b.. - level because of the fan-in restrictions. - For example, two-level implementation of the following minimized function,. - For example, the decomposition of the function. - A rectangle (R, C), where R and C are sets of rows and columns, respectively, is a sub- matrix of the cokernel cube matrix such that for each row r i [ R and each column c j [ C, the entry (r i , c j ) of the cokernel matrix is nonzero. - For example, in Table 3.3 the rectangle fR(1, 6), C(1, 2)g indicates intersection between the kernels corresponding to rows 1 and 6. - Figure 3.54 shows the multi- level implementation of the circuit based on the following expressions:. - Figure 3.56 shows the implementation of the EX-OR gate.. - A direct implementation of the function is shown in Figure 3.59.. - The operation of the multiplexer can be described by the function. - In this expression each of the f(i 1 , i 2. - FIGURE 3.63 Multiplexer implementation of the function f (A, B, C, D, E) ¼ A ¯ B¯C¯ þ AB ¯ C¯D¯ þ A ¯ C¯D þ ABC ¯ D þ AE þ B ¯ CE¯ þ C ¯ E.. - The operation of the demultiplexer can be described by the function table shown in Figure 3.64b. - The implementation of the demultiplexer using NAND gates and inverters is shown in Figure 3.64c.. - If the input line in Figure 3.64 is set to logic 0 (i.e., I ¼ 0), the 1-to-4 demultiplexer will act as a decoder. - The NAND– NAND implementation of the sum and the carry-out is shown in Figure 3.66.. - The implementation of the expression for s i and c 0 using NOR gates is shown in Figure 3.68. - Carry-in FIGURE 3.68 Implementation of the full adder using NOR gates.. - The implementation of the above expressions are shown in Figure 3.75b.. - The implementations of the expressions for D and B are shown in Figure 3.76c. - The outputs of the inverter will be 10110. - TABLE 3.9 The 9’s Complement of BCD Digits. - The logic diagram of the 9’s complement circuit is shown in Figure 3.78. - Figure 3.80 shows a simple numerical example of the multiplication. - in the output of the OR gate driven by the minterm,. - FIGURE 3.86 Logic diagram of the programmed PLA.. - Derive the canonical sum-of-products form of the following functions:. - Derive the kernels and cokernels of the following function:. - The behavior of the latch circuit can be represented by the truth table of Figure 4.4a. - Figure 4.5b shows the truth table of the NAND latch. - As can be seen from the truth table of the latch (Fig. - In order to guarantee that valid data is produced at the output of a flip-flop after a maximum clock-to-output delay time (i.e., the time from the rising edge of the clock to the time valid data is available on the output), the input data must not violate the specified setup and hold times. - Figure 4.11b shows the timing diagram of the D flip-flop. - Table 4.1 summarizes the operation of the D flip-flop. - The characteristics of the D flip-flop can be represented by the following equation (Fig. - TABLE 4.1 Function Table of the D Flip-Flop. - The function table of the flip-flop is shown in Figure 4.16b. - As mentioned previously, in a synchronous sequential circuit the state transition (i.e., the change in the outputs of the flip-flops) occurs in synchronization with a pulse. - these also determine the next state of the circuit. - The behavior of the circuit is determined by the following equations:. - Figure 4.24 illustrates the Moore model of the sequential circuit.. - FIGURE 4.29 State table of the equivalent Mealy-type circuit.. - The state diagram of the circuit can be derived from its state table and is shown in Figure 4.31.. - FIGURE 4.31 State diagram of the circuit of Figure 4.30.. - TABLE 4.3 State Table of the Circuit of Figure 4.30. - The behavior of the circuit is described by the following equations:. - z ¼ xy 1 y 2 þ x y 1 y 2 Draw the state diagram of the circuit.
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